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Altera_Forum
Honored Contributor
12 years agoThanks again. Now I changed the clock in the serial configuration on the right hand side to a much lower frequency and I can see the signals changing as they should. I was previously using the 50MHz clock for this.
My counter signal however which is added as a node is not counting in the window as the signals change. It stays at 00H which is incorrrect. This counter is defined as an integer in the VHDL code. Is there any reason that it is not displaying the counting? I was expecting to see it count to 10 as this is the start and stop storage condition. All the other signals are changing as expected however.