Signal Tap II display signals?

It seems that you are learning.* Figuring things out yourself is part of the learning process.* I am not going to point out anything obvious.* There are a few not so obvious ones I can tell you.

1. You need to learn to verify your design in simulator.* That's part of HDL design flow.

2. If you do use SignalTap to verify as a shortcut of avoiding learning to write testbench, you need to start from beginning: verify one counter and register at a time. Don't start from the end without knowing if circuit leading to the final result is correct.* (Often, the tool is working correctly. Think about your error, not the tool.)* You can add all signals to reduce compilation time since your design is small.* In SignalTap, you can leave the storage qualifier feature on, but disable.* Enable/disable it doesn't require you to recompile, a compilation time saver.* You may find that verifying in simulator will be more productive in long run.* Don't take too much shortcut.

3. Don't use that pulse, freq, as the clock, but as a clock enable signal.* In FPGA, it's never a good idea to use gated clock, unless you know compiler can implement it with special hard clock network circuit on the device.* The timing closure with gated clock is hard.* The compiler is getting better at it.* You cannot rely on it still* Designing a fully synchronized design on simple clock is a key to success in FPGA world.* If learning clock divider is not part of objective, you should be using PLL clock divider instead, a hard device feature.

Have fun learning.