Occasional ContributorSeveral problems encountered when we used LVDS interface on Cyclone 10 GX devices
Hello guys, I have posted one question about LVDS in Programmable Devices group. Here is the link: https://community.intel.com/t5/Programmable-Devices/Why-do-i-get-this-error-when-I-use-lvds/m-p/1619233/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExaN1lUQlI2VDRQNk5JfDE2MTkyMzN8U1VCU0NSSVBUSU9OU3xoSw#M97015
We are keeping testing and debugging our hardware with Cyclone 10 GX devices now. So there are several other problems, which need you help.
1. The termination constrain selection:
In our case, there are three different LVDS input signal types.
1). ADC output differential pairs;
2). LVDS interconnection between other FPGAs. On C10GX side is LVDS-RX.
3). External pulse input pairs.
The above first two items, we know how to add on-chip termination, which is, for example of ADC, input_termination differential constrain as following.
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_A set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_A set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_B set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_B set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_C set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_C set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_D set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_D set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_DCO set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_FCO
We try to add same constrain for above item 3), however, it will work incorrectly with this constrain. But it can work well when we add the following constrain to them:
set_instance_assignment -name XCVR_C10_RX_TERM_SEL R_R1 -to CBA_TRIGGER_3 -entity sep_cs_relay_top set_instance_assignment -name XCVR_C10_RX_TERM_SEL R_R1 -to CBA_TRIGGER_2 -entity sep_cs_relay_top #set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CBA_TRIGGER_3 -entity sep_cs_relay_top #set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CBA_TRIGGER_2 -entity sep_cs_relay_top
This external pulse signal is LVDS differential standard, FPGA logic only uses it as simple trigger pulse, intead of high speed serial data transfer. Could anyone explain what's the reason for this?
2. For ADC serial data deserialize, we implemented bit slip function. You knonw, above ADC has total 8 LVDS channels. So we generated 8 pulse signals and assigned them to each bit slip control input. But the question is that only LSB was assigned succesfully. It means that only the LSB of bit slip control signals was active and it can control for all 8 LVDS channels alignment. Why only the LSB bit slip is required for this function?
