Several problems encountered when we used LVDS interface on Cyclone 10 GX devices

I’m not following the problem with bitslip. When using DPA, you need to bitslip each channel independently and have a known pattern on each channel to detect the word boundary. The DPA behavior can lead to any 2 channels being a bit apart in the word alignment. When not using DPA, it is common to use the same bit slip pulse for all of the channels since every channel uses the same capture clock. There must be reasonably low channel to channel skew in the PCB layout for it to work properly, but you should see data in every channel shift a bit when pulsing the bitslip port, assuming the single signal has been wired up to all of the ports correctly.

I don’t know what we are supposed to be looking at in the signal tap capture. You said there are 8 channels, but the data is grouped in 12 bit chunks and we don’t know the deserialization factor. You need a description for what each signal represents, and I find it’s helpful when debugging the LVDS IP to have at least one of the groups expanded so you can see what is happening for each channel. You should see the data shift in the direction of MSB to LSB one bit for each bitslip pulse: