Several problems encountered when we used LVDS interface on Cyclone 10 GX devices

Let’s say you have a deserialization factor of 4 and the serial data is 1000. On the parallel side you want to see 1000, but let’s say you see 0100 instead. The first bitslip pulse will move the parallel data to 0010, then another pulse will get you 0001, and finally a 3rd pulse would get you to the desired 1000.

That seems to be what we are seeing on the top row of the signal tap file. For a 12 bit sequence, they show 400, which would be 0100 0000 0000. A single bit slip pulse would move that 1 to the right, so you’d have 0010 0000 0000 which is 200. As you continue to move that 1 to the right, you get 100, 080, 040, 020, etc. I don’t know why these are in 12 bit groups, the max SERDES depth is 10 unless this is SERDES in LEs, not the hard IP. I also don’t know why the sequence goes from 040 to 800, unless they changed the incoming data, or reset the bit slip. Unless you know the incoming data pattern and deserialization factor, signal tap captures don’t help.