Forum Discussion

Altera_Forum

Honored Contributor

9 years ago

ROM and RAM connection

Hello,

Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM

This is code for ROM

LIBRARY ieee;    USE ieee.std_logic_1164.all;
     use STD.textio.all;
    ENTITY sync_rom IS
     PORT (
      clock: IN std_logic;
      address: IN integer range 0 to 511;
      data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255    
     );
    END sync_rom;
    ARCHITECTURE rtl OF sync_rom IS
    BEGIN
    PROCESS (clock)
     BEGIN
     IF rising_edge (clock) THEN
      CASE address IS
       WHEN 0 => 
            data_a_i <= 128;
            data_b_q <= 128;
       WHEN 16 => 
             data_a_i <= 128;
             data_b_q <= 128;
         WHEN 70 =>
             data_a_i <= 128;
             data_b_q <= 128;      
         WHEN 400 => 
             data_a_i <= 128;
             data_b_q <= 128;
       WHEN OTHERS  => 
              data_a_i <= 0;
             data_b_q <= 0;
        
      END CASE;
     END IF;
     END PROCESS;
END rtl;

This is code for RAM

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dp_ram_rbw_scl is
  generic (
    DATA_WIDTH : integer := 256;
    ADDR_WIDTH : integer := 256
    );
  port (
-- common clock
    clk    : in  std_logic;
    -- Port A
    we_a   : in  std_logic;
    addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
    -- Port B
    we_b   : in  std_logic;
    addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end dp_ram_rbw_scl;
architecture rtl of dp_ram_rbw_scl is
  -- Shared memory
  type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
  shared variable mem : mem_type;
begin
-- Port A
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_a <= mem(conv_integer(addr_a));
      if(we_a = '1') then
        mem(conv_integer(addr_a)) := data_a;
      end if;
    end if;
  end process;
-- Port B
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_b <= mem(conv_integer(addr_b));
      if(we_b = '1') then
        mem(conv_integer(addr_b)) := data_b;
      end if;
    end if;
  end process;
end rtl;

after this this I write TOP level entity

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255;
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256;
        
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0);
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
);
         port (
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
--for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
--Signal     data_a_i: integer range 0 to 255; 
--data_b_q_a: std_logic_vector(255 downto 0);--interanal signals
begin
--inst : dp_ram_rbw_scl port map ( addr_a=> addr_a,
--clk=> clk,we_a=>we_a,data_a=>data_a,addr_b=>addr_b,data_b=>data_b,we_b=>we_b); 
q_a<= addr_a and data_a;
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => clock,
                                address =>address,
                                data_a_i =>data_a_i,
                                data_b_q =>data_b_q
                                );
C2: dp_ram_rbw_scl Port map (
                                    clk=>clk,
                                    we_a=>we_a,
                                    addr_a=>addr_a,
                                    data_a =>data_a,
                                    q_a=>q_a,
                                    we_b=>we_b,
                                    addr_b=>addr_b,
                                    data_b =>data_b,
                                    q_b=>q_b
                                );
                                data_a_i<=to_integer ( unsigned (data_a));
                                data_b_q<=to_integer ( unsigned (data_b));
end rtl;

But this code doesnt work/Could you please give me some hints for solution? I want to connect data_a_i(ROM) with data_a(RAM) and data_b_q(ROM) with data_b(RAM)

I get next errors

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_b" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_b" must have actual or default value

37 Replies

Altera_Forum
Honored Contributor
9 years ago
any help)?
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
any help)?
--- Quote End ---

use same type for port map then change type afterwards a required. Normally we do std_logic_vector at interface, signed/unsigned or integer internally
Altera_Forum
Honored Contributor
9 years ago
Could you please give me example in my code/how should i do
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Could you please give me example in my code/how should i do
--- Quote End ---

declare these in top lvel

data_a : std_logic_vector...);
data_a_:i: integer ...;

connect data_a to data_a of c2
assign data_a to data_a_i through conversion:

data_a_i <= to_integer(unsigned(data_a));

connect data_a_i to rom

Altera_Forum

Honored Contributor

9 years ago

Thanks for replay,I changed as you said,but code still has some errors

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
      use ieee.std_logic_signed.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        CLOC: IN std_logic;
        ADD: IN integer range 0 to 511;
        DATA_WIDTHi : integer := 256;
        ADDR_WIDTHi : integer := 256;
          data_a : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
          data_b : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
        data_a_i : integer range 0 to 255;
          data_b_q : integer range 0 to 255;
        clk    : in  std_logic;    
        we_ai   : in  std_logic;
        addr_ai : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_ai   : out std_logic_vector(DATA_WIDTHi-1 downto 0);
        we_bq   : in  std_logic;
        addr_bq : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_bq    : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
        
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
            );
    port(
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal     data_a_i_i: integer range 0 to 255;--interanal signals
Signal     data_b_q_i: integer range 0 to 255;--interanal signals
begin
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i_i,
                                data_b_q =>data_b_q_i
                                );
C2: dp_ram_rbw_scl
Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,
                                    data_a =>data_a,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b,
                                    q_b=>q_bq
                                );
                                            data_a_i_i<= to_integer(unsigned(data_a));
                                            data_b_q_i<= to_integer(unsigned(data_b));
end rtl;

errors

Warning (10036): Verilog HDL or VHDL warning at Vhdl2.vhd(57): object "data_a_i_i" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at Vhdl2.vhd(58): object "data_b_q_i" assigned a value but never read
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_a" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_a" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_b" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_b" must have actual or default value

Altera_Forum
Honored Contributor
9 years ago
you got loads of mistakes. Please try draw diagram of rom, ram, romram with all connections named.
by the way why you haven't used generic for width??
Altera_Forum
Honored Contributor
9 years ago
ok.Im draw all diagrams as you said, and added generic in top level ROMRAM,now my code start running up to 29% and stop due to cant fit design in device error,but when Im open rtl viewer,I see very strange diagram,not like in my paper
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
ok.Im draw all diagrams as you said, and added generic in top level ROMRAM,now my code start running up to 29% and stop due to cant fit design in device error,but when Im open rtl viewer,I see very strange diagram,not like in my paper
--- Quote End ---

don't forget datawidth is bitwidth e.g. 8 (for 0~255). you may have put 256 for width

Altera_Forum

Honored Contributor

9 years ago

I put like this,is it correct?

entity ROMRAM is 
generic(        
		  DATA_WIDTHi : integer := 256;
        ADDR_WIDTHi : integer := 256);

Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
I put like this,is it correct?
entity ROMRAM is generic( DATA_WIDTHi : integer := 256; ADDR_WIDTHi : integer := 256);

--- Quote End ---

is your datawidth 256 bits? No you mean 8

Forum Discussion

ROM and RAM connection

37 Replies

Recent Discussions

Timing analysis - long combinational path

Questa unable to checkout a viewer license

Crash at elaboration

Quartus did not start

Self service license server doesn't work