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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributoryou got loads of mistakes. Please try draw diagram of rom, ram, romram with all connections named.
by the way why you haven't used generic for width??
