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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributorok.Im draw all diagrams as you said, and added generic in top level ROMRAM,now my code start running up to 29% and stop due to cant fit design in device error,but when Im open rtl viewer,I see very strange diagram,not like in my paper
