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Altera_Forum's avatar
Altera_Forum
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10 years ago

ROM and RAM connection

Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Could you please give me example in my code/how should i do

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declare these in top lvel

data_a : std_logic_vector...);

data_a_:i: integer ...;

connect data_a to data_a of c2

assign data_a to data_a_i through conversion:

data_a_i <= to_integer(unsigned(data_a));

connect data_a_i to rom