ROM and RAM connection

Thanks for replay,I changed as you said,but code still has some errors

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
      use ieee.std_logic_signed.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        CLOC: IN std_logic;
        ADD: IN integer range 0 to 511;
        DATA_WIDTHi : integer := 256;
        ADDR_WIDTHi : integer := 256;
          data_a : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
          data_b : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
        data_a_i : integer range 0 to 255;
          data_b_q : integer range 0 to 255;
        clk    : in  std_logic;    
        we_ai   : in  std_logic;
        addr_ai : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_ai   : out std_logic_vector(DATA_WIDTHi-1 downto 0);
        we_bq   : in  std_logic;
        addr_bq : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_bq    : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
        
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
            );
    port(
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal     data_a_i_i: integer range 0 to 255;--interanal signals
Signal     data_b_q_i: integer range 0 to 255;--interanal signals
begin
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i_i,
                                data_b_q =>data_b_q_i
                                );
C2: dp_ram_rbw_scl
Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,
                                    data_a =>data_a,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b,
                                    q_b=>q_bq
                                );
                                            data_a_i_i<= to_integer(unsigned(data_a));
                                            data_b_q_i<= to_integer(unsigned(data_b));
end rtl;

Warning (10036): Verilog HDL or VHDL warning at Vhdl2.vhd(57): object "data_a_i_i" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at Vhdl2.vhd(58): object "data_b_q_i" assigned a value but never read
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_a" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_a" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_b" must have actual or default value
Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_b" must have actual or default value