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Altera_Forum's avatar
Altera_Forum
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10 years ago

ROM and RAM connection

Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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any help)?

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use same type for port map then change type afterwards a required. Normally we do std_logic_vector at interface, signed/unsigned or integer internally