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Altera_Forum

Honored Contributor

9 years ago

ROM and RAM connection

Hello,

Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM

This is code for ROM

LIBRARY ieee;    USE ieee.std_logic_1164.all;
     use STD.textio.all;
    ENTITY sync_rom IS
     PORT (
      clock: IN std_logic;
      address: IN integer range 0 to 511;
      data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255    
     );
    END sync_rom;
    ARCHITECTURE rtl OF sync_rom IS
    BEGIN
    PROCESS (clock)
     BEGIN
     IF rising_edge (clock) THEN
      CASE address IS
       WHEN 0 => 
            data_a_i <= 128;
            data_b_q <= 128;
       WHEN 16 => 
             data_a_i <= 128;
             data_b_q <= 128;
         WHEN 70 =>
             data_a_i <= 128;
             data_b_q <= 128;      
         WHEN 400 => 
             data_a_i <= 128;
             data_b_q <= 128;
       WHEN OTHERS  => 
              data_a_i <= 0;
             data_b_q <= 0;
        
      END CASE;
     END IF;
     END PROCESS;
END rtl;

This is code for RAM

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dp_ram_rbw_scl is
  generic (
    DATA_WIDTH : integer := 256;
    ADDR_WIDTH : integer := 256
    );
  port (
-- common clock
    clk    : in  std_logic;
    -- Port A
    we_a   : in  std_logic;
    addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
    -- Port B
    we_b   : in  std_logic;
    addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end dp_ram_rbw_scl;
architecture rtl of dp_ram_rbw_scl is
  -- Shared memory
  type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
  shared variable mem : mem_type;
begin
-- Port A
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_a <= mem(conv_integer(addr_a));
      if(we_a = '1') then
        mem(conv_integer(addr_a)) := data_a;
      end if;
    end if;
  end process;
-- Port B
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_b <= mem(conv_integer(addr_b));
      if(we_b = '1') then
        mem(conv_integer(addr_b)) := data_b;
      end if;
    end if;
  end process;
end rtl;

after this this I write TOP level entity

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255;
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256;
        
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0);
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
);
         port (
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
--for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
--Signal     data_a_i: integer range 0 to 255; 
--data_b_q_a: std_logic_vector(255 downto 0);--interanal signals
begin
--inst : dp_ram_rbw_scl port map ( addr_a=> addr_a,
--clk=> clk,we_a=>we_a,data_a=>data_a,addr_b=>addr_b,data_b=>data_b,we_b=>we_b); 
q_a<= addr_a and data_a;
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => clock,
                                address =>address,
                                data_a_i =>data_a_i,
                                data_b_q =>data_b_q
                                );
C2: dp_ram_rbw_scl Port map (
                                    clk=>clk,
                                    we_a=>we_a,
                                    addr_a=>addr_a,
                                    data_a =>data_a,
                                    q_a=>q_a,
                                    we_b=>we_b,
                                    addr_b=>addr_b,
                                    data_b =>data_b,
                                    q_b=>q_b
                                );
                                data_a_i<=to_integer ( unsigned (data_a));
                                data_b_q<=to_integer ( unsigned (data_b));
end rtl;

But this code doesnt work/Could you please give me some hints for solution? I want to connect data_a_i(ROM) with data_a(RAM) and data_b_q(ROM) with data_b(RAM)

I get next errors

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_b" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_b" must have actual or default value

37 Replies

Altera_Forum
Honored Contributor
9 years ago
you haven't declared signals in top level, you just copied names of your lower level modules.
Altera_Forum
Honored Contributor
9 years ago
On the top level I should you use different names of the signals?When I define entity ROMRAM and the lower entity I should remain the same?
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
On the top level I should you use different names of the signals?When I define entity ROMRAM and the lower entity I should remain the same?
--- Quote End ---

use any name but declare them. The top level does not view signals inside lower modules as declared at top level

Altera_Forum

Honored Contributor

9 years ago

Thanks)I got it)pls say how I can convert std_logic vector and integer?I do it like this but not works

C2: dp_ram_rbw_scl Port map (									clk=>CLOC,
									we_a=>we_ai,
									addr_a=>addr_ai,
									data_a =>data_a_i,
									q_a=>q_ai,
									we_b=>we_bq,
									addr_b=>addr_bq,
									data_b =>data_b_q,
									q_b=>q_bq
								);
								data_a_i<=to_integer ( unsigned (data_a));
								data_b_q<=to_integer ( unsigned (data_b));
end rtl;

Altera_Forum
Honored Contributor
9 years ago
data_i <=to_integer(unsigned(data_s));

is ok if data_i is integer ad data_s is std_logic_vector and you have library numeric_std
Altera_Forum
Honored Contributor
9 years ago
yes.data_i is integer.
data_s is std_logic_vector
Im using library numeric_std
but I have error
Error (10476): VHDL error at Vhdl2.vhd(67): type of identifier "data_a_i" does not agree with its usage as "std_logic_vector" type
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
yes.data_i is integer.
data_s is std_logic_vector
Im using library numeric_std
but I have error
Error (10476): VHDL error at Vhdl2.vhd(67): type of identifier "data_a_i" does not agree with its usage as "std_logic_vector" type
--- Quote End ---

double check your declarations or copy your code snippet here

Altera_Forum

Honored Contributor

9 years ago

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        CLOC: IN std_logic;
        ADD: IN integer range 0 to 511;
        DATA_WIDTHi : integer := 256;
        ADDR_WIDTHi : integer := 256;
        
        clk    : in  std_logic;    
        we_ai   : in  std_logic;
        addr_ai : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_ai   : out std_logic_vector(DATA_WIDTHi-1 downto 0);
        we_bq   : in  std_logic;
        addr_bq : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_bq    : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
        
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
            );
    port(
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal     data_a_i: integer range 0 to 255;--interanal signals
Signal     data_b_q: integer range 0 to 255;--interanal signals
begin
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i,
                                data_b_q =>data_b_q
                                );
C2: dp_ram_rbw_scl Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,
                                    data_a =>data_a_i,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b_q,
                                    q_b=>q_bq
                                );
                                data_a_i<=to_integer(unsigned(data_a)); 
                                data_b_q<=to_integer(unsigned(data_b));
end rtl;

Altera_Forum
Honored Contributor
9 years ago
c2 data_a is std_logic_vector and you are connecting it to integer..
Altera_Forum
Honored Contributor
9 years ago
ok/what should i do.how to convert it or?

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ROM and RAM connection

37 Replies

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