ROM and RAM connection

Hello,

Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM

This is code for ROM

LIBRARY ieee;    USE ieee.std_logic_1164.all;
     use STD.textio.all;
    ENTITY sync_rom IS
     PORT (
      clock: IN std_logic;
      address: IN integer range 0 to 511;
      data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255    
     );
    END sync_rom;
    ARCHITECTURE rtl OF sync_rom IS
    BEGIN
    PROCESS (clock)
     BEGIN
     IF rising_edge (clock) THEN
      CASE address IS
       WHEN 0 => 
            data_a_i <= 128;
            data_b_q <= 128;
       WHEN 16 => 
             data_a_i <= 128;
             data_b_q <= 128;
         WHEN 70 =>
             data_a_i <= 128;
             data_b_q <= 128;      
         WHEN 400 => 
             data_a_i <= 128;
             data_b_q <= 128;
       WHEN OTHERS  => 
              data_a_i <= 0;
             data_b_q <= 0;
        
      END CASE;
     END IF;
     END PROCESS;
END rtl;

This is code for RAM

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dp_ram_rbw_scl is
  generic (
    DATA_WIDTH : integer := 256;
    ADDR_WIDTH : integer := 256
    );
  port (
-- common clock
    clk    : in  std_logic;
    -- Port A
    we_a   : in  std_logic;
    addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
    -- Port B
    we_b   : in  std_logic;
    addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end dp_ram_rbw_scl;
architecture rtl of dp_ram_rbw_scl is
  -- Shared memory
  type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
  shared variable mem : mem_type;
begin
-- Port A
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_a <= mem(conv_integer(addr_a));
      if(we_a = '1') then
        mem(conv_integer(addr_a)) := data_a;
      end if;
    end if;
  end process;
-- Port B
  process(clk)
  begin
    if(clk'event and clk = '1') then
      q_b <= mem(conv_integer(addr_b));
      if(we_b = '1') then
        mem(conv_integer(addr_b)) := data_b;
      end if;
    end if;
  end process;
end rtl;

after this this I write TOP level entity

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255;
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256;
        
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0);
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
);
         port (
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
--for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
--Signal     data_a_i: integer range 0 to 255; 
--data_b_q_a: std_logic_vector(255 downto 0);--interanal signals
begin
--inst : dp_ram_rbw_scl port map ( addr_a=> addr_a,
--clk=> clk,we_a=>we_a,data_a=>data_a,addr_b=>addr_b,data_b=>data_b,we_b=>we_b); 
q_a<= addr_a and data_a;
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => clock,
                                address =>address,
                                data_a_i =>data_a_i,
                                data_b_q =>data_b_q
                                );
C2: dp_ram_rbw_scl Port map (
                                    clk=>clk,
                                    we_a=>we_a,
                                    addr_a=>addr_a,
                                    data_a =>data_a,
                                    q_a=>q_a,
                                    we_b=>we_b,
                                    addr_b=>addr_b,
                                    data_b =>data_b,
                                    q_b=>q_b
                                );
                                data_a_i<=to_integer ( unsigned (data_a));
                                data_b_q<=to_integer ( unsigned (data_b));
end rtl;
        

But this code doesnt work/Could you please give me some hints for solution? I want to connect data_a_i(ROM) with data_a(RAM) and data_b_q(ROM) with data_b(RAM)

I get next errors

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_a" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "addr_b" must have actual or default value

Error (10346): VHDL error at Vhdl2.vhd(70): formal port or parameter "data_b" must have actual or default value