Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
...
Altera_ForumHonored Contributor
Honored Contributoryes.data_i is integer.
data_s is std_logic_vector Im using library numeric_std but I have error Error (10476): VHDL error at Vhdl2.vhd(67): type of identifier "data_a_i" does not agree with its usage as "std_logic_vector" type
