Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

ROM and RAM connection

Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

data_i <=to_integer(unsigned(data_s));

is ok if data_i is integer ad data_s is std_logic_vector and you have library numeric_std