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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- On the top level I should you use different names of the signals?When I define entity ROMRAM and the lower entity I should remain the same? --- Quote End --- use any name but declare them. The top level does not view signals inside lower modules as declared at top level
