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Altera_Forum's avatar
Altera_Forum
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10 years ago

ROM and RAM connection

Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks)I got it)pls say how I can convert std_logic vector and integer?I do it like this but not works 

C2: dp_ram_rbw_scl Port map (									clk=>CLOC,
									we_a=>we_ai,
									addr_a=>addr_ai,
									data_a =>data_a_i,
									q_a=>q_ai,
									we_b=>we_bq,
									addr_b=>addr_bq,
									data_b =>data_b_q,
									q_b=>q_bq
								);
								data_a_i<=to_integer ( unsigned (data_a));
								data_b_q<=to_integer ( unsigned (data_b));
end rtl;