Quartus won't let me use Signal Tap. Can't elaborate "sld_hub:auto_hub"

Unfortunately, I'm not getting this error either when I compile your design.

What are the messages that appear just before the error you posted, especially the warnings that are mentioned above? They can help clue into where in your design is the issue.

Have you tried compiling with Signal Tap disabled? Is that successful?

#iwork4intel

Hello,

When I disable the signal tap it works with no problem. I checked the warnings, but there isn't seem to be anything unusual. But here is the list of warnings I get:

warnings:

--------------------------------------

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(39): object "FT601_debug_signal" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(47): object "usb_rx_busy" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(51): object "usb_tx_busy" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(56): object "rx_DATA_BE" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(57): object "tx_DATA" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(58): object "TX_DATA_BE" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(67): object "rx_FIFO_ae" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(68): object "rx_FIFO_af" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(69): object "rx_FIFO_empty" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(70): object "rx_FIFO_full" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(77): object "rx_BE_FIFO_empty" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(78): object "rx_BE_FIFO_full" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(83): object "tx_FIFO_aclr" assigned a value but never read

Warning (10540): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(18): used explicit default value for signal "FT_RESET_N" because signal was never assigned a value

Warning (10540): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(19): used explicit default value for signal "FT_WAKEUP" because signal was never assigned a value

Warning (10541): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(37): used implicit default value for signal "debug_signal" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.

Warning (10036): Verilog HDL or VHDL warning at FT601_245_FIFO.vhd(54): object "FT_WR_buf" assigned a value but never read

Warning (10492): VHDL Process Statement warning at FT601_245_FIFO.vhd(65): signal "reset_n" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

Warning (11175): Alt_sld_fab.alt_sld_fab: This module has no ports or interfaces

This is very strange. Comparing side-by-side the messages you got against what I got when the design compiled successfully, the main issue seems to be the synthesis of alt_sld_fab, which is an encrypted IP used to connect Signal Tap to the JTAG. So normally, I would recommend reinstalling everything, blah, blah, blah but you've already tried that and it still didn't work.

What is the directory path to where this project is located? If it's really long, try shortening the path and removing any spaces that may be in it. Longshot: also check write permissions just in case. Maybe something in the OS is preventing reading or writing of the IP files.

I noticed that your .stp file is located in the output_files directory for some reason. I doubt that's the issue since it compiled fine for me, but try bringing it up one level to the project directory.

Try these things and report back. This is really strange.

#iwork4intel

Based on your suggestion I tried to move the project to different location, but it didn't make any difference. I even tried moving directly to C driver (the shortest possible path), but didn't work. My quaruts is installed at "C:\intelFPGA_lite" I think this is the default location.

The location of .stp file also didn't make any difference.

I checked the permissions, there is nothing preventing OS from writing, reading or anything else to quartus directories.

What really strage is that I tried to run it on different computers and I get the same error. A few people here had the same problem and none of them was solved. BUMMER!

I don't know what to blame? Encryption???

What do I do next? I think someone from intel called me today, it was early in the morning and I was driving and couldn't talk. They didn't call me back. :D

Well, the next thing I'd try is recreating the .stp file from scratch because it's what causes alt_sld_fab to be synthesized. First, disable Signal Tap in the project settings, then close and reopen the project. Then, create a brand new .stp file, choosing to enable Signal Tap in the project when you save the file. Again, I didn't have a failure when I compiled with the existing .stp, so I don't know if this will do anything for you.

I'm not sure why, but maybe even the signals you are tapping are causing the issue. See if you can compile with an empty .stp file. If that works, re-add the signals you're tapping group by group. I doubt this is the issue or will do anything, but I don't know what else to try.

Is the board with the device you are using currently attached to the machine you are using to compile? Again, that shouldn't cause any issues, but try disconnecting it before compilation.

#iwork4intel

I am going to try setting up a virtual environement and try to running on linux.

Maybe that'll work.

Hi Alrepen,

I tried to compile the design using latest version 19.1 Lite and cannot reproduce the error. Even with and without stp and did it several times. I suspect this error might be related to Quartus SW itself at your side could be due to installation issue etc. Did you have multiple Quartus installed in your machine? Not recommended to do so. Also make sure your OS compatible and up to date. I will try to run it in Linux if it is OS issue.

Hi Alperen,

Few references I found hopefully would be helpful related to your issue. Refer to links below for details

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07292013_807.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd08062013_201.html

Hi Alperen,

This workaround might be little bit weird try to change your operating system language of your language to English according to this reference forum case and recompile it.

https://forums.intel.com/s/question/0D50P00003yyTZPSA2/altsldfab-error

Absolutely nothing worked.

Not a even single thing changed.