Quartus won't let me use Signal Tap. Can't elaborate "sld_hub:auto_hub"

Hello,

When I disable the signal tap it works with no problem. I checked the warnings, but there isn't seem to be anything unusual. But here is the list of warnings I get:

warnings:

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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(39): object "FT601_debug_signal" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(47): object "usb_rx_busy" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(51): object "usb_tx_busy" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(56): object "rx_DATA_BE" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(57): object "tx_DATA" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(58): object "TX_DATA_BE" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(67): object "rx_FIFO_ae" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(68): object "rx_FIFO_af" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(69): object "rx_FIFO_empty" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(70): object "rx_FIFO_full" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(77): object "rx_BE_FIFO_empty" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(78): object "rx_BE_FIFO_full" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at USB3_if.vhd(83): object "tx_FIFO_aclr" assigned a value but never read

Warning (10540): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(18): used explicit default value for signal "FT_RESET_N" because signal was never assigned a value

Warning (10540): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(19): used explicit default value for signal "FT_WAKEUP" because signal was never assigned a value

Warning (10541): VHDL Signal Declaration warning at FT601_245_FIFO.vhd(37): used implicit default value for signal "debug_signal" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.

Warning (10036): Verilog HDL or VHDL warning at FT601_245_FIFO.vhd(54): object "FT_WR_buf" assigned a value but never read

Warning (10492): VHDL Process Statement warning at FT601_245_FIFO.vhd(65): signal "reset_n" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

Warning (11175): Alt_sld_fab.alt_sld_fab: This module has no ports or interfaces