Quartus Router Congestion

What is your clocking setup, and do you have the design constrained properly? Timing constraints that are too tight can cause the tools to work way too hard, duplicate logic, etc.

Result is not fed into multiplier, no way to do another math.

Yes I have 100 MHz target, divider have 6 clock of latency.

750bit x512 ram built with registers is HUGE. thats nearly 400k registers alone! No wonder routing is congested!

I used VHDL 2008 fixed point division with retiming (and stages of registers at output) but performance isn't so great..

My experience used to be Altera and Xilinx passes were similar. The fact that it takes 14 hours to synthesize for a Cyclone V design makes me think something is wrong, as that seems wildly out of proportion. They've always had fast compile times and over an hour seems long to me. (General statement though. I remember one design that was about that size, but the RTL would originally make something about 10x that size and due to nets tied off it would get reduced down to 1/10th that size. This was how the user coded their design, but the synthesis times were significantly higher than design of similar size)

Compiling with Quartus using LPM_DIV with Pipeline is better