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Honored Contributor
Honored ContributorQuartus Router Congestion
Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_ForumHonored Contributor
Honored ContributorCompiling with Quartus using LPM_DIV with Pipeline is better
http://www.alteraforum.com/forum/attachment.php?attachmentid=11715&stc=1 I have too low frequency but during fitting I have hibernated PC and when resumed today compilation time was wrong (counted also when pc was turned off) and then skipped some optimizations.. Info (170236): Routing optimizations have been running for 12 hour(s) Info (170242): 197139 out of 213944 signals have been routed. Info (170238): 27703 interconnect resources are used by multiple signals. Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170200): Optimizations that may affect the design's timing were skipped Never hibernate during compilation.. PS: Powerplay report that Routing Dynamic Power is more than Block Thermal Power, routing power is used only at configuration?
