Quartus Router Congestion

My experience used to be Altera and Xilinx passes were similar. The fact that it takes 14 hours to synthesize for a Cyclone V design makes me think something is wrong, as that seems wildly out of proportion. They've always had fast compile times and over an hour seems long to me. (General statement though. I remember one design that was about that size, but the RTL would originally make something about 10x that size and due to nets tied off it would get reduced down to 1/10th that size. This was how the user coded their design, but the synthesis times were significantly higher than design of similar size)