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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I used VHDL 2008 fixed point division with retiming (and stages of registers at output) but performance isn't so great..

I use also multipliers in another part of design but with Cyclone V A9 there are a lot of it.. seem a good idea to try.