Quartus Router Congestion

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I used VHDL 2008 fixed point division with retiming (and stages of registers at output) but performance isn't so great..

I use also multipliers in another part of design but with Cyclone V A9 there are a lot of it.. seem a good idea to try.

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I would always trust the lpm_divide megafunction over retimed dividers. its quite easy to just instantiate an lpm divide manually and do type conversion on the in/output. It would avoid the need for synplify (which has never done a better job than quartus - which was admitted by the synplify reps when they visited - this was several years ago though).