Quartus QSYS in QSF keeps generating verilog (but i need VHDL)

Hi!

First of all, the question:

Is there any way to tell quartus (not qsys!) to generate VHDL(and not verilog) for a qsys system?

Now the details:

I've added a QSYS file to my Quartus Settings File (QSF). After that, quartus does elaborate the qsys file and generate the output in <myProjectFolder>/db/ip/*.

set_global_assignment -name QSYS_FILE ../../some/path/to/NiosSystem.qsys

When i use the qsys gui to generate the synthesis output, i can choose between verilog and VHDL, i need to choose VHDL to get round this quartus bug:

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05212011_256.html

The qsys gui does respect this setting which is also saved to the qsys file:

 <parameter name="hdlLanguage" value="VHDL" />

When i run a quartus compile flow from the quartus gui, this setting is not respected. I endup with verilog HDL files which i can't use (without further processing) for synthesis.

Thx!