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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus QSYS in QSF keeps generating verilog (but i need VHDL)

Hi! First of all, the question: Is there any way to tell quartus (not qsys!) to generate VHDL(and not verilog) for a qsys system? Now the details: I've added a QSYS file to my Quartus ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Two questions:

- can you confirm that this is a qsf setting or does this endup in some sort of quartus registry setting? If it's the latter, it's quite useless because you can't easily share this with collegues and furthermore if you're doing automated builds (headless pc), you're lost.

- i guess there's no way to force vhdl in 13.1?