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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus QSYS in QSF keeps generating verilog (but i need VHDL)

Hi! First of all, the question: Is there any way to tell quartus (not qsys!) to generate VHDL(and not verilog) for a qsys system? Now the details: I've added a QSYS file to my Quartus ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello,

Do you have the .qsys file or the qip file in your quartus project?

I have the .qip file in mine and only generate the verilog code from inside the qsys tool. When I compile the project the code does not get regenerated.

The following is from the Quartus handbook volume 1 section 5

"If you want file generation to occur as part of the Quartus II software's compilation, you should include

the .qsys file in your Quartus II project. If you want to manually control file generation outside of the

Quartus II software, you should include the .qip file in your Quartus II project."

Kevin