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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus QSYS in QSF keeps generating verilog (but i need VHDL)

Hi! First of all, the question: Is there any way to tell quartus (not qsys!) to generate VHDL(and not verilog) for a qsys system? Now the details: I've added a QSYS file to my Quartus ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Try Assignments -> Settings -> IP Settings and change it to VHDL. I am working on a design where this isn't working, but I think there's another layer of complication that makes this different. Please post if this works. Thanks.