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SMore11's avatar
SMore11
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7 years ago

Quartus Prime Lite stuck during compilation (analysis & synthesis step)

Hello,

I have troubles when I compile a project of mine on Quartus Prime Lite 18.0 with, as target FPGA device, a MAX10 (10M08DAF256C8GES). The compiler is stuck during the elaboration of a component (its architecture consists of ~ 500 lines of VHDL code and it does not use arithmetic multiplicators). The progress of the "Analysis & Synthesis" step reaches 47% and it stays frozen like that for 10 minutes. There is no special message on the log. I decided to stop the compilation. In a previous version of my code (with a little less lines of codes), the full compilation went through OK in 5 minutes (~4000 elements are used and I can upload the .sof to the FPGA and run it). I would like to know which can be the cause of this behavior, if you have already experienced something similar. Thank you for any help.

11 Replies

  • JOHI's avatar
    JOHI
    Icon for Contributor rankContributor
    7 years ago

    ​Hello,

    If you ask this question to Intel the first answer you would likely get:

    Does Q18.1 have a similar problem?

    This is the standard reply from all software suppliers.

    If you would like me to test it on my licensed 18.1, feel free to include a .QAR in your reply.

    Some of the problems I got with the free version (crashes) were solved with the licensed version.

    Best Regards,

    Johi.

  • SMore11's avatar
    SMore11
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello, thank you for your answers. Deleting db and incremental_db didn't help, unfortunately. I am a bit reluctant to upgrade to Quartus Lite 18.1 now. Since I had no problem with compilation of other VHDL sources, I suspect the one for which I have problems is too complex to be synthesized and traps the Quartus compiler into an infinite loop and something like that. I can see that during the compilation the RAM used by Quartus on my PC increases until it reaches the maximum amount (and my PC gets frozen). I will try to optimize my code.

  • CLa_R's avatar
    CLa_R
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    I have the same problem.

    Quartus II 17.0 is stuck for hours (more than 8 hours) on 47% analisys. I am compiling for Cyclone IV E (ep4ce10...).

    I noticed that, in my design (a MISP type CPU mono clock), if I wired the final MUX selection signal with control signal, the compile is stuck on 47%.

    If I fix the select signal of final MUX to a value (eg. VCC), my design compile in few seconds. But...why?

    I am trying my design also with quartus 19.1 and the problem is the same.

      • Hakeen's avatar
        Hakeen
        Icon for New Contributor rankNew Contributor
        5 years ago

        here the code:

        // create module
        module blink(
        input wire clk, // 50MHz input clock
        output wire [7:0] LED // array of 8 LEDs
        );

        // create a binary counter
        reg [31:0] cnt; //32 bit counter

        initial begin

        cnt <= 32'h00000000; // start count at zero

        end

        always @(posedge clk) begin

        cnt <= cnt+1; // count up

        end

        //assign LEDs to bits 28 through 21 of the counter

        assign LED = cnt[28:21];

  • Karlis_Susters's avatar
    Karlis_Susters
    Icon for New Contributor rankNew Contributor
    3 years ago

    I had the exact same analysis and synthesis stuck on 47% issue, I solved it by setting "Allow register merging" to "Off" in Compiler settings -> advanced synthesis settings.

    If that doesn't work, might be worth literally toggling every synthesis setting on that page and seeing if that works. Then narrow it down to the one setting that causes the problem by toggling a half, then a quarter, ...

    Karlis

    • TheGil's avatar
      TheGil
      Icon for New Contributor rankNew Contributor
      2 years ago

      This works for me! Thank you

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    If possible try to share projects file, We will try to replicate the scenario. If it is bug we can file a bug report for you.

    As johi said use latest version of quartus (Quartus 18.1 lite) and try.

    Regards

    Anand

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    Try trashing the db and incremental_db folders and recompile. This fixes most compilation issues.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    I seriously doubt that a MAX 10 design would be the cause here. If you were compiling for a top-of-the line Stratix 10 device, then certainly.

    Can you post your code? What is the difference between the version that successfully compiled and the version that is not compiling?

  • SMore11's avatar
    SMore11
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    6 years ago

    Hello,

    Thank you for your replies and suggestions. I think the problem comes from my computer: I tried to compile a project that was fine until some days ago, and now it gets frozen at 47% of Analysis & Synthesis. I will fix this computer or get a new one.