Quartus Prime Lite stuck during compilation (analysis & synthesis step)

Hello, thank you for your answers. Deleting db and incremental_db didn't help, unfortunately. I am a bit reluctant to upgrade to Quartus Lite 18.1 now. Since I had no problem with compilation of other VHDL sources, I suspect the one for which I have problems is too complex to be synthesized and traps the Quartus compiler into an infinite loop and something like that. I can see that during the compilation the RAM used by Quartus on my PC increases until it reaches the maximum amount (and my PC gets frozen). I will try to optimize my code.