New ContributorQuartus Version : (Quartus Prime 22.1std) Standard Edition
FPGA model: Cyclone IV E (EP4CE55F23C8)
When establishing DDR2 IP, the following error occurs. Please tell me how to effectively solve this problem. Thank you.
error message
Super Contributor
New ContributorHi,
I saw the two log files,but i still can not find the error.
Provide two files below and look forward to your reply.
Below is make_qii_design_errors.log
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Nov 4 22:28:17 2023
Info: Command: quartus_sh -t C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl
Info:
Info: *************************************************************************
Info: Altera External Memory Interface IP Example Design Builder
Info:
Info: Type : Quartus Prime Project
Info: Family: Cyclone IV E
Info: Device: EP4CE55F23C8
Info:
Info: This script takes ~1 minute to execute...
Info: *************************************************************************
Info:
Info: Generating example design files...
Error (23031): Evaluation of Tcl script C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 4631 megabytes
Error: Processing ended: Sat Nov 4 22:29:34 2023
Error: Elapsed time: 00:01:17
Error: Total CPU time (on all processors): 00:00:22
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --synthesis --output-directory=. --family=$family --part=$device >>& ip_generate.out"
(file "C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl" line 92)
------------------------------------------------
And this is make_sim_design_errors
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Nov 4 22:29:35 2023
Info: Command: quartus_sh -t C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl
Info:
Info: *************************************************************************
Info: Altera External Memory Interface IP Example Design Builder
Info:
Info: Type : Simulation Design
Info: Family : Cyclone IV E
Info: Language: VERILOG
Info:
Info: This script takes ~1 minute to execute...
Info: *************************************************************************
Info:
Info: Generating example design files...
Error (23031): Evaluation of Tcl script C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 4631 megabytes
Error: Processing ended: Sat Nov 4 22:32:10 2023
Error: Elapsed time: 00:02:35
Error: Total CPU time (on all processors): 00:00:30
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --simulation=$lang --output-directory=. --family=$family --part=$device >>& ip_generate.out"
(file "C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl" line 104)
------------------------------------------------
Regular ContributorHello,
Thank you for submitting your question in Intel Community.
I'm Adzim, will assist you in this thread.
Are you able to generate the IP only?
Can you generate the example design through the tcl script?
Is there any example design that has been successfully generated from same machine?
Regards,
Adzim
New ContributorAre you able to generate the IP only?
Unfortunately, I cannot successfully use Quartus 22.1 to generate DDR2 IP. When I generated the IP, I encountered the above error, but I currently don’t know what the error means.
New ContributorCan you generate the example design through the tcl script?
I'm sorry, I don't understand what you mean. Can you explain it in more detail?
Thanks!
Regular ContributorHi,
Can you check if there any error if you generate the IP only by clicking on Generate HDL button at bottom right of the IP GUI?
The error messages above related to example design generation.
Generating the IP only does not generate the example design.
The tcl scripts are located in the example design directory. Default: ..\alt_mem_if_civ_ddr2_emif_0_example_design\
There is a readme.txt file that describes how to use the tcl script.
make_qii_design.tcl is for generating synthesis design.
make_sim_design.tcl is for generating simulation design.
Are you able to generate other EMIF IP such as UniPHY DDR3 example design?
Regards,
Adzim
New ContributorCan you check if there any error if you generate the IP only by clicking on Generate HDL button at bottom right of the IP GUI?
It can succeed but contains the following warning
"Warning: ddr2_ip.alt_mem_if_civ_ddr2_emif_0.phy.RESET_REQUEST: Associated reset sinks not declared"
Are you able to generate other EMIF IP such as UniPHY DDR3 example design?
Because I am using cyclone iv, it does not have the UniPhy function.
Regular ContributorHi,
I have tried to generate the ddr2 example design at my end but I don't encounter similar issue during the generating process.
What is the OS version and build that you are currently using?
Can you try to generate the design in shorter path name?
Can you check if you are able to generate the design in Quartus lite edition?
Regards,
Adzim
New ContributorWhat is the OS version and build that you are currently using?
My computer operating system is window11, this time I use quartus prime lite 22.1
Can you try to generate the design in shorter path name?
The path length should be quite short.
Can you check if you are able to generate the design in Quartus lite edition?
When using the lite version, the following screen will be stuck when generating the sample file. It seems that it cannot be finished.
Regular ContributorAs we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
