Quartus ignores clock constraints in SDC file

Question

Hello,My project is a very slow (fastest clock is 3.6864MHz) cpld design. There are 5 different clock dividers in the design that generate clocks from 1.8432MHz to 1Hz. I have put clock constraints for each of these clocks into the SDC file:create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 }create_clock -name {clock_divider:CDIV1|clk_out} -period 542.000 -waveform { 0.000 271.000 }create_clock -name {clock_divider:CDIV2|clk_out} -period 1084.000 -waveform { 0.000 542.000 }create_clock -name {clock_divider:CDIV3|clk_out} -period 17300.000 -waveform { 0.000 8650.000 }create_clock -name {clock_divider:CDIV4|clk_out} -period 100000.000 -waveform { 0.000 50000.000 }create_clock -name {clock_divider:CDIV5|clk_out} -period 100000.000 -waveform { 0.000 50000.000 }For the slowest 2 clocks, I just used 10kHz, they are actually slower. In the Timing analyzer, I tried to define the clock divider outputs as generated clocks. But these constraints were rejected and not saved to the SDC file.When I compile, I get the following warnings:Warning (332060): Node: clock_divider:CDIV3|clk_out was determined to be a clock but was found without an associated clock assignment.Info (13166): Register Uart8Transmitter:UART_TX1|serial_out is being clocked by clock_divider:CDIV3|clk_outWarning (332060): Node: clock_divider:CDIV2|clk_out was determined to be a clock but was found without an associated clock assignment.Info (13166): Register clock_divider:CDIV3|clk_out is being clocked by clock_divider:CDIV2|clk_outWarning (332060): Node: clock_divider:CDIV5|clk_out was determined to be a clock but was found without an associated clock assignment.Info (13166): Register seconds_counter[0] is being clocked by clock_divider:CDIV5|clk_outWarning (332060): Node: clock_in_3p6864mhz was determined to be a clock but was found without an associated clock assignment.Info (13166): Register clock_divider:CDIV1|clk_out is being clocked by clock_in_3p6864mhzWarning (332060): Node: clock_divider:CDIV4|clk_out was determined to be a clock but was found without an associated clock assignment.Info (13166): Register clock_divider:CDIV5|clk_out is being clocked by clock_divider:CDIV4|clk_outWarning (332061): Virtual clock clock_in_3p6864mhz is never referenced in any input or output delay assignment.Can anyone tell me what is going on here? Is there a low frequency limit for the timing analyzer that is higher than my fastest clock?Thanks,Jim

jch4416 · Answer

Adding the Clock Summary Table from the Timing Analyzer

sstrell · Answer

None of those constraints have targets.  You've given them all names but they are not targeted to anything in your design, so they've all been designated as virtual clocks.  I'm assuming that the names you've given the clocks are really their targets in the timing netlist.  And yes, you should be using create_generated_clock for the internal ones.  So your first couple constraints should look something like:
create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports clock_in_3p6864mhz]
create_generated_clock -name {CDIV1] -divide_by 2 -source [get_pins CDIV1|clk_in] [get_pins CDIV1|clk_out]
I'm guessing at the name for the input pin of the clock divider, but I think you get the idea.  Use the Name Finder tool, accessible through the GUI dialog boxes for SDC constraints you can access from the Edit menu of the Quartus Text Editor, to search for the exact pin names in the timing netlist.

jch4416 · Answer

Thank you, this makes a lot of sense.
Between some of my dividers there are global buffers to distribute the generated clock. Do I need a generated clock constraint on each GBUF, or is the buffer taken into account automatically?
In the case of the main clock, clk_in_3p6864mhz,  it comes into the cpld on a global pin so the fitter automatically uses a GBUF on it. For the first divider, should the source name be clk_in_3p6864mhz or clk_in_3p6864mhz~combout? I found the later name in the list of nets and I assume it is the implicit GBUF output.
Thanks

jch4416 · Answer

I was trying to implement your advice and had a problem. After I divide the main clock, I send it to a GBUF.  Then I use a wire declaration to name the GBUF output, which I feed into the next clock divider. The problem is that when I search for the wire name (cpld_master_clock) using get_pins, get_nets, and get_keepers it isn't there.  I also can't find any pin or net for CDIV2.clk_in.  
I assume the compiler is renaming things as it fits the design, but how do I find the source for CDIV2 to create a generated clock constraint? My code is below.
--------------------------
wire cpld_master_clock;
-
-
-
GLOBAL GBUF1 (master_clock_out, cpld_master_clock);
clock_divider #(UART_RX_CLK_DIVISOR) CDIV2 (.clk_in(cpld_master_clock), .clk_out(uart_rx_clock));

khaichein_y_intel · Answer

Hi,

Can you share the design QAR for investigation? To generate the QAR, click on Project &gt; Archive Project &gt; Archive.

Thanks
Best regards,
KhaiY

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Quartus ignores clock constraints in SDC file

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