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jch4416
Occasional Contributor
Occasional ContributorQuartus ignores clock constraints in SDC file
Hello, My project is a very slow (fastest clock is 3.6864MHz) cpld design. There are 5 different clock dividers in the design that generate clocks from 1.8432MHz to 1Hz. I have put clock constraints...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
KhaiY
