Occasional Contributor
Super ContributorNone of those constraints have targets. You've given them all names but they are not targeted to anything in your design, so they've all been designated as virtual clocks. I'm assuming that the names you've given the clocks are really their targets in the timing netlist. And yes, you should be using create_generated_clock for the internal ones. So your first couple constraints should look something like:
create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports clock_in_3p6864mhz]
create_generated_clock -name {CDIV1] -divide_by 2 -source [get_pins CDIV1|clk_in] [get_pins CDIV1|clk_out]
I'm guessing at the name for the input pin of the clock divider, but I think you get the idea. Use the Name Finder tool, accessible through the GUI dialog boxes for SDC constraints you can access from the Edit menu of the Quartus Text Editor, to search for the exact pin names in the timing netlist.
Occasional ContributorI was trying to implement your advice and had a problem. After I divide the main clock, I send it to a GBUF. Then I use a wire declaration to name the GBUF output, which I feed into the next clock divider. The problem is that when I search for the wire name (cpld_master_clock) using get_pins, get_nets, and get_keepers it isn't there. I also can't find any pin or net for CDIV2.clk_in.
I assume the compiler is renaming things as it fits the design, but how do I find the source for CDIV2 to create a generated clock constraint? My code is below.
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wire cpld_master_clock;
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GLOBAL GBUF1 (master_clock_out, cpld_master_clock);
clock_divider #(UART_RX_CLK_DIVISOR) CDIV2 (.clk_in(cpld_master_clock), .clk_out(uart_rx_clock));
Regular ContributorHi,
Can you share the design QAR for investigation? To generate the QAR, click on Project > Archive Project > Archive.
Thanks
Best regards,
KhaiY
