Quartus ignores clock constraints in SDC file

I was trying to implement your advice and had a problem. After I divide the main clock, I send it to a GBUF. Then I use a wire declaration to name the GBUF output, which I feed into the next clock divider. The problem is that when I search for the wire name (cpld_master_clock) using get_pins, get_nets, and get_keepers it isn't there. I also can't find any pin or net for CDIV2.clk_in.

I assume the compiler is renaming things as it fits the design, but how do I find the source for CDIV2 to create a generated clock constraint? My code is below.

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wire cpld_master_clock;

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GLOBAL GBUF1 (master_clock_out, cpld_master_clock);

clock_divider #(UART_RX_CLK_DIVISOR) CDIV2 (.clk_in(cpld_master_clock), .clk_out(uart_rx_clock));