Occasional Contributor
Super ContributorNone of those constraints have targets. You've given them all names but they are not targeted to anything in your design, so they've all been designated as virtual clocks. I'm assuming that the names you've given the clocks are really their targets in the timing netlist. And yes, you should be using create_generated_clock for the internal ones. So your first couple constraints should look something like:
create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports clock_in_3p6864mhz]
create_generated_clock -name {CDIV1] -divide_by 2 -source [get_pins CDIV1|clk_in] [get_pins CDIV1|clk_out]
I'm guessing at the name for the input pin of the clock divider, but I think you get the idea. Use the Name Finder tool, accessible through the GUI dialog boxes for SDC constraints you can access from the Edit menu of the Quartus Text Editor, to search for the exact pin names in the timing netlist.
Occasional ContributorThank you, this makes a lot of sense.
Between some of my dividers there are global buffers to distribute the generated clock. Do I need a generated clock constraint on each GBUF, or is the buffer taken into account automatically?
In the case of the main clock, clk_in_3p6864mhz, it comes into the cpld on a global pin so the fitter automatically uses a GBUF on it. For the first divider, should the source name be clk_in_3p6864mhz or clk_in_3p6864mhz~combout? I found the later name in the list of nets and I assume it is the implicit GBUF output.
Thanks
