Forum Discussion
jch4416
Occasional Contributor
Occasional ContributorQuartus ignores clock constraints in SDC file
Hello, My project is a very slow (fastest clock is 3.6864MHz) cpld design. There are 5 different clock dividers in the design that generate clocks from 1.8432MHz to 1Hz. I have put clock constraints...
jch4416Occasional Contributor
Occasional ContributorAdding the Clock Summary Table from the Timing Analyzer
