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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus filters out essential parts of state machine?

Hi,

Recently faced very strange issue in my design.

I have state machine, which goes through multiple steps, and at the end there is kind of "Delay" state and "SetReady" state...

Problem is that these states are optimized away for some reasons...

I can understand that from analyzer point of view they probably do not have any value, but as a result all timings are screwed.

After days of debugging I found that if SignalTap is enabled, everything works perfectly (Heisenbug?) - that leads me to solution, which if really crappy, but worked - I introduced external signal "ExternalPullUp" and make it as conditions for all transitions between states. Ideally I don't want to ask customers to have additional signal on their PCBs for that purposes.

Next thing I tried is I create internal counter and after 100 clocks I set ExternalPullUp to '1' instead of external pin, kind of enabling device.

That worked for a while but now I got this issue back again.

I am not really expert in optimization, maybe you can suggest something (which works for Xilinx as well)

"ExternalPullUp" pin solution is last resort, will go live if I could not fix it properly.

P.S.

I can attach code, but it is useless as it came from VHDL generator and not really human readable.

Thank you.

Regards,

Evgeny.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The synthesisor will remove code if it determines it is unused, or states that it thinks are unreachable. Without the code we cannot really comment - but did you simulate the design before putting it on a baord?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    The synthesisor will remove code if it determines it is unused, or states that it thinks are unreachable. Without the code we cannot really comment - but did you simulate the design before putting it on a baord?

    --- Quote End ---

    Yes, I put it through simulation, it fails with same thing as board, which is at least promising :)

    Exactly the same code works fine in different project..

    I will attach project when I get home..

    (it is for quartus 9, my board is very old)

    thanks,

    Evgeny.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If it fails in RTL simulation (not gate level) then that tells you there is something wrong with some code somewhere.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    If it fails in RTL simulation (not gate level) then that tells you there is something wrong with some code somewhere.

    --- Quote End ---

    Apparently it is, thanks. I found timing issue which only happened in that particular project.

    With the root problem, which is related to optimization:

    Originally I had my UART driver, which works fine for some random time ( 1 - 10 minutes, and then suddenly stuck.

    ExternalPullUp solution which preserves all states unoptimized, or running with SignalTap and monitoring some states fixes it.

    I suspect it should be something wrong with my code, but I spent 3 weeks debugging it and gave up.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Have you provided timing specs for Timequest to do timing analysis in your design? or are there asynchronous circuits that are causing the issues? Using async circuits and latches are not recommended precisely for timing issues that cannot be caught in simulation or timing analysis.