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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus filters out essential parts of state machine?

Hi, Recently faced very strange issue in my design. I have state machine, which goes through multiple steps, and at the end there is kind of "Delay" state and "SetReady" state... Problem is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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If it fails in RTL simulation (not gate level) then that tells you there is something wrong with some code somewhere.

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Apparently it is, thanks. I found timing issue which only happened in that particular project.

With the root problem, which is related to optimization:

Originally I had my UART driver, which works fine for some random time ( 1 - 10 minutes, and then suddenly stuck.

ExternalPullUp solution which preserves all states unoptimized, or running with SignalTap and monitoring some states fixes it.

I suspect it should be something wrong with my code, but I spent 3 weeks debugging it and gave up.