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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus filters out essential parts of state machine?

Hi, Recently faced very strange issue in my design. I have state machine, which goes through multiple steps, and at the end there is kind of "Delay" state and "SetReady" state... Problem is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If it fails in RTL simulation (not gate level) then that tells you there is something wrong with some code somewhere.