Qsys Custom Component Problem

I am experiencing a problem using Qsys while adding a custom component into

a design and wanted to ask if others have seen this issue. I have run three

experiments to link in a custom component using both SOPC and Qsys under

Quartus II V11.1. One of the Qsys methods still fails.

The experiments are as follows:

1) Using SOPC and adding the new core by instantiating it in the top level

HDL source. Here, I add the Avalon MM-Slave used to link the new component

to NiosII in the SOPC System and link the I/O ports provided in the System

module to the new core within the top level HDL source file. The PLL is

also instantiated at the top level providing both a fast cpu clock and a

slow peripheral clock. The slow peripheral clock is used by multiple

SOPC peripherals and the new core. With this configuration, I can

successfully access the new core's registers.

2) Using Qsys and adding the new core by including the top level HDL file when

creating the custom component. The PLL is instantiated at the top level,

but the new core is not. This version also allows for successful access

to the new core's registers.

3) Using Qsys and adding the new core by instantiating it in the top level

HDL source. This version does not work. Just like the SOPC version, the

Avalon MM-Slave is configured to export the I/O ports needed to link the new

core at the top level. The Qsys generation does correctly place these I/O

ports in the system module. The PLL is also instantiated at the top level.

When running this version, the NiosII cpu and other peripherals that use

the slower clock still work, but the new core's registers are not accessible.

I always read 0's from the core's control register. As a small experiment,

I tried disconnecting the reset to the new core in case that was a problem.

That still didn't work.

My conclusion's at this point are that either Qsys no longer allows for the

core to be instantiated from the top level, I'm still making a mistake in

how I've tried to configure the MM-Slave's ports to the top level, or

Qsys has a problem. If Qsys is intended to still allow for the capability

to instantiate custom cores at the top level, I would still like to

pursue getting this to work that way.