Qsys Custom Component Problem

I've narrowed down the issue to a problem with Qsys.

After setting up SignalTap, I learned that the resulting Avalon Bus cycle is not lasting as

long as expected. The custom core creates a two clock bus cycle by deasserting the waitrequest_n

(high) on the second clock cycle. When viewing the Avalon bus cycle in SignalTap, it shows that

chipselect and write are going inactive prior to the deassertion of the waitrequest_n control.

Since the actual register writes occur one clock cycle after the deassertion of the waitrequest_n

control while chipselect is still active, no register writes are occurring. Hence the registers

always reads back as zero's.

When viewing the bus cycle in the Custom Component editor, it indicates that chipselect does

not deassert until one clock cycle after waitrequest_n deassertion. However Qsys is not

working that way in the system and interprets the signal as being a positive active waitrequest.

To get the design running, I modified the top level hdl source by inverted the waitrequest_n

signal from the new core before routing it back to the Qsys module. Now the registers are

accessable and the core runs.