Qsys Custom Component Problem

I'm certian that the custiom core in question is being included in the overall FPGA build.

I do see the ports I've configured it for in the Qsys "HDL Example" tab. I've also opened

the verilog source that Qsys generates and can see the ports defined there with the

appropriate bus widths. I've re-run Qsys generation after each time that anything was

changed in the Qsys configuration.

When building the three of the examples that I mentioned, all of them report virtually the

same device utilization for the custom core.