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Altera_Forum
Honored Contributor
14 years agoYou can see the potential port changes prior to generation by using the "HDL Example" tab. You can verify that your ports are exported.
(At least this is my experience with Qsys in 11.1)You can see the potential port changes prior to generation by using the "HDL Example" tab. You can verify that your ports are exported.
(At least this is my experience with Qsys in 11.1)