qmegawiz generated SRAM simulation model broken

I've tried 21.1 and 21.1.1, the results are the same.

Here is the pertinent data from the generated variation file:

module psu_mgmt_sram (
clock,
data,
rdaddress,
wraddress,
wren,
q);

input clock;
input [31:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];

altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "TRUE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;


endmodule

I have tried multiple configurations, with and without byte enables. I haven't tried them all because ideally byte enables work the best for me. Although I will try a byte interface on the write path and 32 bit on the read path next.

When I use Platform Designer to generate a simulation model, there is one big difference that I can see in Questa.

The signal mentioned in the variation file, "subwire0" is missing from the module top level.

In the rams that are working that signal shows the read data.

I can't see into the firm macro with Questa.

It looks to me like qmegawiz / Platform Designer are having problems with Cyclone V SRAM.

I'll keep searching for a work around, but I would like someone to try to reproduce this.

Thanks much for your support.