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BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

qmegawiz generated SRAM simulation model broken

I've tried 21.1 and 21.1.1, the results are the same. Here is the pertinent data from the generated variation file: module psu_mgmt_sram ( clock, data, rdaddress, wraddress, wren, q); input c...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

Tested the code posted with a testbench. I'm able to see the signal sub_wire0 in Questa check image attached.

May be can try go to sim tab -> right-click -> Add to -> Wave -> All items in region and below

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thanks much.

I can't actually see sub_wire0 in the objects windows when I select any of the RAMs that I've attempted to create recently. But it does exist in the old RAMs that were made a while ago.

The odd thing is, I changed a sea of registers to SRAM a few weeks ago to see if it would save much space in the design and it did not and it failed to meet timing. The RAM that I created for that worked fine, no issues, but I went back to the registers so I wouldn't have to re-pipeline the design to add an output register to the SRAM.

Here is a picture of questa showing the missing wire:

sub_wire0 is missing

This morning I tried removing the entire simulation folder to force Platform Designer to do a complete rebuild and it didn't help.

I know I've done something foolish. I just can't figure out what it is.