Forum Discussion
BrianM
Occasional Contributor
Occasional Contributorqmegawiz generated SRAM simulation model broken
I've tried 21.1 and 21.1.1, the results are the same.
Here is the pertinent data from the generated variation file:
module psu_mgmt_sram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input c...
ShengN_altera
Super Contributor
Super ContributorCould you attach the design file for testing out?
BrianMOccasional Contributor
Occasional ContributorI gave up and put in a synthesizable verilog dual port SRAM recommended by intel here: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/examples/download/true_dpram_sclk_v.zip
It simulates properly and appears to synthesize properly, although I have to verify that it is inferring ram.
