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BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

qmegawiz generated SRAM simulation model broken

I've tried 21.1 and 21.1.1, the results are the same. Here is the pertinent data from the generated variation file: module psu_mgmt_sram ( clock, data, rdaddress, wraddress, wren, q); input c...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

It looks like q is the top-level signal. Why are you looking at sub_wire0? And q_b is the output from the block RAM itself.

BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thanks for the quick reply.

The q output is always 32'hzzzzzzzz

I can see the writes to the RAM happening, but readback always produces zzzzzzzz.

I noticed that sub_wire0 exists in the RAM model that works that was created a long time ago for the original FPGA. But for the new RAM model, there is no sub_wire0.