Forum Discussion
BrianM
Occasional Contributor
Occasional Contributorqmegawiz generated SRAM simulation model broken
I've tried 21.1 and 21.1.1, the results are the same.
Here is the pertinent data from the generated variation file:
module psu_mgmt_sram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input c...
ShengN_altera
Super Contributor
Super ContributorHi,
Yes, the true dual port ram is inferred. Can check from:
Compilation Report -> Analysis & Synthesis -> RAM Summary
Compilation Report -> Fitter -> Resource Section -> RAM Summary
Thanks,
Best Regards,
Sheng
