Pseudo Random Bit generator with VHDL

Here's a PRBS tutorial with source code:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

You can also use a linear chirp signal and pulse compression for distance measurement (even if it is only a 1-bit output).

Cheers,

Dave

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The easiest way would be with a linear feedback shift register: http://en.wikipedia.org/wiki/linear_feedback_shift_register

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Thank you I'll try it.

Dave, I'm trying to understand and test this code, yet I keep receiving errors do I have to create two separate VHDL files in QUARTUS to run this, one for the testbench and one for the LFSR? When does it mean that is a TESTBENCH? My goal is to generate a random set of bits in order to output a random voltage signal trough the GPIO pins in my DE2 board then I will connect it to a transmitter circuit. This circuit depends on a MOSFET, Resistor, and the transducer. Yet, my first step is understand how to build a LFSR to generate the signal

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity PRNG22 is

generic ( width : integer := 32 );

port (

clk : in std_logic;

random_num : out std_logic_vector (width-1 downto 0) --output vector

);

end PRNG22;

architecture Behavioral of PRNG22 is

begin

process(clk)

variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');

variable temp : std_logic := '0';

begin

if(rising_edge(clk)) then

temp := rand_temp(width-1) xor rand_temp(width-2);

rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);

rand_temp(0) := temp;

end if;

random_num <= rand_temp;

end process;

END Behavioral;

------------------------------------------------------

--The test bench for the code is given below:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY testbench IS

ARCHITECTURE behavior OF testbench IS

--Input and Output definitions.

signal clk : std_logic := '0';

signal random_num : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 1 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: entity work.random generic map (width => 4) PORT MAP (

clk => clk,

random_num => random_num

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

END

Now I got the code down to 4 errors yet I do not what to change.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity PRNG22 is

generic ( width : integer := 8 );

port (

clk : in std_logic;

random_num : out std_logic_vector (width-1 downto 0) --output vector

);

end PRNG22;

architecture Behavioral of PRNG22 is

--Input and Output definitions.

signal clk : std_logic := '0';

signal random_num : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time = '1' ;

begin

variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');

variable temp : std_logic = '0';

-- Instantiate the Unit Under Test (UUT)

uut: entity work.random generic map (width => 4) PORT MAP

(

clk => clk,

random_num => random_num

);

PROCESS_1: process(clk)

begin

if(rising_edge(clk)) then

temp := rand_temp(width-1) xor rand_temp(width-2);

rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);

rand_temp(0) := temp;

end if;

random_num <= rand_temp;

end process PROCESS_1;

------------------------------------------------------

--The test bench for the code is given below:

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

END Behavioral;

You have messed it up on yourself.

use the original Dave'c code but run the testbench code as top level in your simulator. This testbench will then call up your design as a component.

Hi Francisco,

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I'm trying to understand and test this code, yet I keep receiving errors

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Start by running the existing testbenches.

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do I have to create two separate VHDL files in QUARTUS to run this, one for the testbench and one for the LFSR?

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Quartus is for *synthesis* only. A testbench is for simulation only, and is run in Modelsim.

If you have written C-code before; you component is equivalent to your C-code, while the testbench is equivalent to a unit test.

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My goal is to generate a random set of bits in order to output a random voltage signal trough the GPIO pins in my DE2 board then I will connect it to a transmitter circuit.

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You will not get a random voltage. You will get a stream of 0s and 1s that occur in a random order.

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This circuit depends on a MOSFET, Resistor, and the transducer.

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Make sure your GPIO can drive the MOSFET correctly, eg., a power MOSFET requires more current than a GPIO can supply.

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Yet, my first step is understand how to build a LFSR to generate the signal

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Simply instantiate the LFSR component.

Here's what you need to do.

1. Start Modelsim.
2. Change directory to where ever you unzipped the zip file
    Modelsim> cd {c:\temp\lfsr_tutorial_src\prbs}
3. Source the simulation script
    Modelsim> source scripts/sim.tcl
4. Run the testbench
    Modelsim> lfsr_tb

Now read the code (VHDL and Tcl scripts), and try to understand it.

Cheers,

Dave