Altera_ForumHonored Contributor12 years agoPseudo Random Bit generator with VHDL May anyone give me a hint how to create a Pseudo Random Bit Generator with VHDL and/or Block Diagrams with an ALTERA DE2 Board for a Distance Sensor. The "Random" bits are to be used to generate a se...Show More
Altera_ForumHonored Contributor12 years agonote also quartus does not support testbench code, use modelsim
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: